1. Field of the Invention
The invention relates to a method of fabricating a multilevel interconnect process, and particularly relates to a method of fabricating a metal interconnect process used for avoiding poisoned vias.
2. Description of the Related Art
In integration circuit process for semiconductor devices, the interconnects are provided between two devices to allow electrical connection. The present metal interconnect comprises multilevel metal layer to connect the devices in the circuit, since the density of integrated circuits has increased and the function has become more complicated.
The inter-metal dielectric layer (IMD) is used for isolating an upper metal layer and a lower metal layer. The upper and lower metal layers are connected by vias.
In the conventional multilevel interconnect process, an inter-metal dielectric layer is formed to cover a substrate having metal lines thereon. Thereafter, via openings are formed in the inter-metal dielectric layer by photolithography and etching, and then the via openings are filled with a metal plug layer to form vias. Other metal deposition processes, photolithography and etching are performed.
Organic polymer material that has a dielectric constant lower than the dielectric constant of silicon oxide is used as the inter-metal dielectric layer in deep sub-micron processes, in order to increase the device performance and reduce the resistance-capacitance time delay effect.
However, the organic polymer material that has a low dielectric constant is damaged while the photoresist is being removed by oxygen plasma. In the above method of fabricating the metal interconnects, after the via openings are formed by etching the inter-metal dielectric layer composed of the organic polymer material, the organic polymer material exposed by the sidewall of the via openings is damaged.